Processing FPGA

Zebra Rapixo CoF Product Reference Guide

Processing FPGA

Zebra Rapixo CoF100 features an on-board real-time processing FPGA device (Processing FPGA), which can be configured to offload and even accelerate the most compute-intensive part of typical image processing applications, without generating additional data traffic within the host computer (Host). The Processing FPGA on the CoF100 is a highly customizable Xilinx Kintex UltraScale+ (KU15P).

Before the Processing FPGA can process grabbed images, they must be stored in on-board memory. If images stored in Host memory are required, they can be streamed directly to the Processing FPGA for processing. Images and other data resulting from processing can be stored in on-board memory or streamed to the Host.

The maximum peak bandwidth for images streamed directly to/from Host memory is 16Gbyte/sec, as well as for images streamed to/from on-board memory.

Possible processing operations

To use the Processing FPGA, you must configure it with an FPGA configuration that defines the appropriate functionality. An FPGA configuration is a code segment that is used to program an FPGA. The following diagram shows the configurable FPGA components in an FPGA configuration.

You would typically use standard Zebra FPGA configurations. You can also choose to implement processing on your own, using the Zebra FPGA Developers Toolkit (FDK) and C++. If required, Zebra’s FPGA design services can be employed to develop an application-specific FPGA configuration.

Once the Processing FPGA is programmed, you can then make use of its functionality using Aurora Imaging Library. Refer to Using Aurora Imaging Library with a Processing FPGA chapter in the Aurora Imaging Library User Guide for more information.